Recently, a high-performance CMISFET, which includes an n-type and a p-type MISFET metal gate electrode having different work functions, has been gaining attention. For example, Article 1 (Samavedam et al., IDEM Tech. Dig., (2002) p. 443) discloses a technique of manufacturing a CMISFET, wherein by forming a TiN film for the p-type MISFET electrode throughout the entire surface of a wafer; removing the TiN film from the n-type MISFET region; and then depositing a TaSiN and a poly silicon film, the CMISFET is made to include a p-type MISFET region having a TiN electrode and an n-type MISFET region having a TaSiN electrode. Moreover, Article 2 (Terai et al. VLSI Symp. Tech. Dig., (2005) p. 68) discloses a technique of manufacturing a CMISFET in which an n-type MISFET has a metal gate electrode made of NiSi and a p-type MISFET has a metal gate electrode made of Ni3Si.
However, in the technique disclosed in Article 1, since the TiN film formed in the n-type MISFET region needs to be removed during the manufacturing process, a gate insulating film residing below the TiN film may be subject to damage. Further, in Article 2, an HfSiON film is used as a gate insulating film, and a flat band voltage difference (relating to a work function difference) between the n-type MISFET having the NiSi metal gate electrode and the p-type MISFET having the Ni3Si metal gate electrode is as small as 0.25 V, thereby making the technique impractical.
Meanwhile, Japanese Patent Laid-Open Application No. 2002-217313 (hereinafter, referred to as “Patent Document 1”) discloses a technique of manufacturing a CMISFET. In Patent Document 1, a cobalt layer and a silicon layer are sequentially formed on a gate dielectric layer and then parts of the silicon layer are removed. Thereafter, the resultant structure is heat-treated to locally form silicide, leaving cobalt silicide portions and cobalt portions both serving as gate electrodes. Thereafter, by performing further device forming processes, the CMISFET including n-type MISFET regions having cobalt silicide gate electrodes and p-type MISFET regions having cobalt gate electrodes are fabricated. In this technique, since it is not required to remove a layer that has been directly formed on the gate insulating film, the gate insulating film is prevented from being damaged. Further, relatively large theoretical work function difference can be obtained in the n-type MISFET and the p-type MISFET.
However, upon reviewing by the inventors of the present invention, the technique of Patent Document 1 proves to be hardly a practical one. To be specific, after forming the cobalt silicide and the cobalt portions to be functioned as gate electrodes, further processes for forming, e.g., source electrodes, drain electrodes and the like are performed. As a result, the gate electrodes experience relatively high temperatures, which reduces the work function difference between the gate electrodes.
As discussed above, despite the demand to obtain a technique capable of achieving a practical level of a work function difference between gate electrodes of an n-type and a p-type MISFET region without causing damages on an underlying gate insulating film, no such technique has been realized.